United Process Versapro Betriebsanweisung PDF herunterladen (Seite 48)

48 Important Product Information

GFK-1671P

Open Issues and Problems

Store/Load/Clear/Write Flash, EEPROM/Equality Issues

ID Description

CR71034

Failure to achieve logic equal after load and verify of default program with VersaMax

Nano/Micro.

Details: Clear logic in PLC. Load logic. Verify logic but logic remains unequal. Since the

logic is just loaded, the verify step should say that the logic is equal.

Resolution: After loading an auto-configured VersaMax Nano/Micro, you should store the

program and configuration back to the PLC, which will cause the logic to be equal..

CR71325/

CR71929

Store problems after clear/load when using Ethernet module on 90-30 PLCs.

Details: VersaPro is connected to a 90-30 PLC via an Ethernet connection.

1) Clear hardware configuration or clear all on the PLC. Clear succeeds, you remain

connected.

2) Load hardware from the PLC. Load succeeds.

3) Open standalone HWC. The CMM 321 Ethernet module does not appear, a blank slot

appears in its place. This is expected since the hardware configuration has been cleared. The

Ethernet module should still communicate since it will keep its IP address. However, the

clearing of hardware configuration will reset the Ethernet module making it unable to

communicate for a short period of time.

4) Store hardware configuration to the PLC. Fails with a “0x0005 Message not yet confirmed”

error. If you attempt to store when the Ethernet module is unable to communicate, you will get

a PLC error message.

Resolution: Retry the store operation. The Ethernet module should complete its reset cycle

and communicate again with the programmer.

CR71731

Logic does not become equal when stored to a Series 90 Micro PLC or VersaMax

Nano/Micro PLC unless a Check All is performed.

Details: Store a folder to the PLC. Note that the logic does not become equal in the status bar.

Perform a verify of logic. The Information Window will say MAIN.dec is equal but

_MAIN.pdt is not equal. This results in the inability to get real time updates in the LD editor.

However, after loading the folder back from the PLC into a temp folder, it was verified that

the logic was indeed equal to what had been stored from the previous folder and this time the

status said the folder was equal.

Resolution: The problem does not occur if a “Check All” is performed before storing the

folder.

CR72183

Inequality after load due to Retentive Map issues.

Details: Create a small VersaPro program which contains an ADD function and a COIL. Use

%M00001 as the output of the ADD function. Set the retentiveness of this variable to non-

retentive. Use %M00008 on the COIL. Set the retentiveness of this variable to retentive.

Then delete the COIL. The usage of the %M0008 variable should remain in the VDT.

Compile and store the program. Create a new folder. Load the program you just stored.

Notice the folder once the load is complete remains unequal. The problem is the Retentive

Map is built based on the VDT. The original folder had a usage of %M00008 which was

retentive so the bit was turned ON. However, the second folder when the load was done did

not have this usage of %M0008 in its VDT. There was also no usage of %M00008 in the

code, except for the implicit usage on the output of the ADD function which was set to non-

retentive. Therefore, when the retentive map for the second folder was created the retentive bit

for the %M00008 bit was turned OFF. Leaving the folder in the unequal state.

Resolution: If the second folder created from the load from the PLC is stored and then loaded

the folder will remain equal with the PLC.

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